уровень на a15 PCI 0,00В всегда. На 71 пине

уровень на a15 PCI 0,00В всегда.
На 71 пине MIO (PWROK) в дежурном режиме 0,15В, после нажатия pwrsw 3,18В
На 30 пине MIO (LRESET) 0,00В всегда.
По поводу VRMPWRGD - на cpu есть напряжение, на asp0905 нет даташита.

The PCIRST# pin is generated under two conditions:
• PLTRST# active

• BCTRL.SBR (D30:F0:Offset 3Eh:bit 6) set to 1
The integrated LAN controller uses the PCIRST# or the PWROK signal as an indication
to ignore the PCI interface. Following the deassertion of PCIRST#, the LAN controller
PCI Configuration Space, MAC configuration, and memory structure are initialized while
preserving the PME# signal and its context.

When asserted, PWROK is an indication to the ICH7 that
core power has been stable for 99 ms and that PCICLK has been
stable for 1 ms. An exception to this rule is if the system is in S3HOT, in
which PWROK may or may not stay asserted even though PCICLK may
be inactive. PWROK can be driven asynchronously. When PWROK is
negated, the ICH7 asserts PLTRST#.