PCI Clock. This pin receives a buffered host clock divided-by-2, 3, or 4 to create 33
MHz. This clock is used by all of the VT82C694X logic that is in the PCI clock
domain. This clock input must be 33 MHz maximum to comply with PCI
specification requirements and must be synchronous with the host CPU clock, HCLK,
with an HCLK:PCLK frequency ratio of 2:1, 3:1, or 4:1 as shown in the table below.
The host CPU clock must lead the PCI clock by 1.5 ± 0.5 nsec.
Typical Clock Frequency Combinations
увлекательное однако чтение: даташит на 694х
PCI Clock. This pin receives a buffered host clock divided-by-2, 3, or 4 to create 33
MHz. This clock is used by all of the VT82C694X logic that is in the PCI clock
domain. This clock input must be 33 MHz maximum to comply with PCI
specification requirements and must be synchronous with the host CPU clock, HCLK,
with an HCLK:PCLK frequency ratio of 2:1, 3:1, or 4:1 as shown in the table below.
The host CPU clock must lead the PCI clock by 1.5 ± 0.5 nsec.
Typical Clock Frequency Combinations
Rx68[1:0] Mode Host Clock AGP Clock PCI Clock
00 .............2x.. 66 MHz .......66 MHz .....33 MHz
01 .............3x .100 MHz ......66 MHz .....33 MHz
10 .............4x. 133 MHz ......66 MHz .....33 MHz
11 .............Reserved
DRAM Operating Frequency Faster Than CPU
0 DRAM Same As or Equal to CPU......... default
1 DRAM Faster Than CPU by 33 MHz
Rx68[1-0] Rx69[7-6] CPU / DRAM
00 .............00 ...........66 / 66 (def)
00 .............01 ...........66 / 100†
01 .............10 ..........100 / 66
01 .............00 ...........100 / 100
01 .............01 ...........100 / 133†
1x .............10 ...........133 / 100
1x .............00 ...........133 / 133
†Rx53[6] must also be set to 1 for DRAM > CPU
заявленного множителя 5х не зрю
Добавлено спустя 19 часов 16 минут 9 секунд:
Дататашит на 694х ревизии новее 101 , а точнее 120 нарыл только в виде упоминания/пустой ссылки
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